Digital design / FPGA
Hardware packet processor with Hamming error correction in VHDL
A modular RTL packet processor that receives serial data, repairs single-bit errors with a hardware Hamming decoder, and executes operations through an ALU and a finite-state-machine control unit. Simulated and verified in ModelSim.
- Stack
- VHDL · FPGA · ModelSim · RTL design · Hamming ECC
- Team
- Built with Parsa Bishe.
- Area
- Digital design / FPGA
What it does
- Serial-in parallel-out and parallel-in serial-out shift registers form the boundary between the transceiver bus and the internal word registers.
- Hamming encoder and decoder blocks detect, isolate and correct bit inversions at run time.
- A parameterised ALU handles arithmetic, logic and data routing.
- An FSM control unit sequences multiplexer routing, read/write handshakes and opcode execution.
- An 8 × 32-bit RAM block provides local caching while payloads are processed.
My part
Mahbod BemaniCham led digital design and the control unit architecture; Parsa Bishe led verification, the ECC pipeline and synthesis.